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US Semiconductor R&D Initiatives Readying for Launch

JUN 27, 2023
The Commerce Department’s new CHIPS R&D Office is preparing to stand up the National Semiconductor Technology Center funded by last year’s CHIPS and Science Act. Complementary initiatives are also underway across several federal agencies.
Will Thomas
Spencer R. Weart Director of Research in History, Policy, and Culture
A chip developed by the National Institute of Standards and Technology that is used to measure the performance of memory devices used by artificial intelligence algorithms.

A chip developed by the National Institute of Standards and Technology that is used to measure the performance of memory devices used by artificial intelligence algorithms.

(B. Hoskins / NIST)

The CHIPS and Science Act’s semiconductor R&D initiatives are gaining steam, with the Commerce Department announcing this month that its new CHIPS R&D Office will be directed by Lora Weiss, senior vice president for research at Penn State University. She will be responsible for ensuring the success of the initiatives’ centerpiece, the National Semiconductor Technology Center, which the department anticipates establishing later this year.

The NSTC will have a startup budget of more than $3 billion with additional billions to follow, all of which is insulated from the annual appropriations process. By statute, the center will be operated as a public-private consortium. The CHIPS R&D Office further specified in a strategy document in April that the center will be an independent nonprofit entity with a headquarters and a geographically distributed network of “affiliated technical centers.”

On top of the NSTC, the CHIPS R&D Office is tasked with organizing a National Advanced Packing Manufacturing Program, up to three new Manufacturing USA institutes for semiconductors, and a semiconductor metrology program within the National Institute of Standards and Technology. In addition, complementary initiatives are underway at the Defense Department, Department of Energy, and National Science Foundation.

Plans coalesce for industry-spanning technology center

Because semiconductor manufacturing requires deep technical sophistication, the CHIPS and Science Act’s R&D initiatives are regarded as essential to the sustained success of the act’s manufacturing incentives, which are likewise ramping up. The act is providing $39 billion to support subsidies, loans, and loan guarantees through the Commerce Department, which opened its first call for applications in February. And in March, the IRS released a notice of proposed rulemaking for the tax credits the act authorized, which will reimburse up to 25% of private investments in facilities, with no ceiling on the total amount of credits available.

The April strategy document notes that applicants for the Commerce Department incentives are expected to also contribute to the NSTC, which is envisioned as an important node within an “ecosystem” of manufacturing, industrial R&D, academic research, and workforce development. A principal goal in setting the center up will be to ensure it attracts broad participation from players in a fiercely competitive industry by advancing their collective interests while safeguarding proprietary knowledge.

The location and structure of the NSTC headquarters and its technical centers are key matters yet to be determined. According to the strategy document, the headquarters will be an administrative center and “prominent gathering place,” and may also be co-located with R&D and prototyping facilities. The technical centers are envisioned as industrial-style facilities, but with an emphasis on “flexibility and availability” rather than “unit cost optimization.” The strategy document states, “The scope and quality [of the centers’ work] will exceed what is feasible for universities, semiconductor startups, federal R&D facilities, and even some corporate R&D laboratories.”

Another crucial issue is the NSTC’s governance. The document states, “The department desires to create an NSTC that can be agile, fast-moving, flexible, responsive to industry and researcher needs, and accountable to taxpayers. The integrity of the NSTC is paramount, and it is essential that it is viewed throughout the ecosystem as neutral, trusted, and science-driven.” Striking such balances will ultimately be the responsibility of a CEO overseen by a board of trustees that will itself be named by a selection committee the Commerce Department has just appointed.

Industrial players have bought into the NSTC concept and formed major coalitions to shape its implementation. The American Semiconductor Innovation Coalition has more than 200 members, including companies such as AMD, GlobalFoundries, Google, IBM, Microsoft, Nvidia, Samsung, Micron, and Analog Devices, as well as an array of universities and national labs. The Semiconductor Alliance includes Intel, Micron, and Analog Devices, and it is led by an arm of the MITRE Corporation, a nonprofit federal contractor.

Once the CHIPS R&D Office solicits proposals to operate the NSTC, these groups are likely to be main contenders. ASIC argues its governance structure is “uniquely positioned” for the NSTC and that it can stand up NSTC facilities in “as little as six months.” While the Semiconductor Alliance has fewer members, MITRE currently manages six Federally Funded R&D Centers and Intel is planning a major new manufacturing complex in Ohio, with an investment potentially reaching $100 billion, as well as R&D hubs and manufacturing facilities in Europe.

Commerce Department R&D office gearing up

Lora Weiss

Lora Weiss is the incoming director of the Commerce Department’s CHIPS R&D Office.

(Patrick Mansell / Penn State Office of Strategic Communications)

In addition to selecting the operators of the NSTC, the CHIPS R&D Office will oversee $11 billion the CHIPS and Science Act is providing in total for the center and other institutions the office is standing up.

Lora Weiss is taking a two-year leave from Penn State to assume the role of office director. Weiss joined the university in 2019 having previously worked at Georgia Tech, including as deputy director and interim director of the Georgia Tech Research Institute, a University-Affiliated Research Center funded by the Army. She holds a doctorate in acoustics and is an expert in robotics, autonomous control systems, and uncrewed vehicles.

The office’s deputy director will be Eric Lin, who has been serving as interim director and was previously director of NIST’s Material Measurement Laboratory.

Lin delivered updates on CHIPS R&D Office activities at a meeting earlier this month of the Industrial Advisory Committee, a body set up last year to provide input from the semiconductor community on the CHIPS initiatives.

Lin said the office aims to release a strategy document late this summer or in early fall covering the National Advanced Packaging Manufacturing Program, which will be more tightly focused than the NSTC, addressing specific problems in fostering a domestic ecosystem for assembling integrated circuits.

Concerning the new Manufacturing USA institutes, Lin noted that the CHIPS R&D Office recently released a summary of responses to a request for information issued in 2021. He said the responses were split on whether there should be a single large institute or multiple focused institutes and indicated the office is currently narrowing down a list of topics it will solicit proposals around in the months ahead.

CHIPS R&D Metrology Program head Marla Dowell, who formerly led NIST’s Communications Technology Laboratory, provided an update on that activity at the meeting. She said the program will support targeted research that complements the other R&D initiatives, focusing on priority areas and seven metrology “grand challenges” that were identified in a report released this month.

DOD, DOE, and NSF initiatives in the works

CHIPS R&D initiatives chart, investment and stages of innovation

A chart illustrating the funding the National Semiconductor Technology Center and other new semiconductor R&D initiatives will provide to bridge early-stage R&D and private-sector product innovation.

(Department of Commerce)

While the CHIPS R&D Office will implement the lion’s share of semiconductor R&D initiatives, other agencies are launching complementary activities.

The Defense Department is receiving $2 billion over five years through the CHIPS and Science Act to supplement the R&D programs the department already supports. The additional funding is specifically for creating a Microelectronics Commons, envisioned as a network of facilities for demonstrating materials, processes, devices, and architectural designs at scale, which are generally not practical for universities or small and mid-size companies to operate.

The department has already solicited proposals for facilities in six application areas: secure edge computing, 5G and 6G technology, artificial intelligence hardware, quantum technology, electronic warfare, and commercial lead-ahead technologies. The National Academies is also conducting a study to advise the department on the value of different public-private partnership models in microelectronics.

The National Science Foundation is receiving $200 million from the act over five years to support workforce development activities in microelectronics and semiconductors. The agency also projects it will also spend over $160 million of its ordinary budget this fiscal year on R&D and workforce development efforts in the area.

The Department of Energy has proposed to establish a series of Microelectronics Science Research Centers as a complement to its existing work in microelectronics. Although the act authorized the centers, it did not provide funding for them, meaning they will have to be funded from DOE’s ordinary budget.

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