Commerce Selects Sites for CHIPS R&D Facilities
Researchers work inside the clean room area at the MacroTechnology Works facility in the ASU Research Park in Tempe, Arizona. The park will host one of the three flagship facilities within the National Semiconductor Technology Center.
Deanna Dent / Arizona State University
The Commerce Department has selected sites for all three flagship R&D facilities within the National Semiconductor Technology Center, a multi-billion-dollar initiative funded by the CHIPS and Science Act to foster domestic semiconductor innovation. The facilities will be in Arizona, California, and New York and aim to bring together researchers from across industry and academia to accelerate semiconductor research and manufacturing. They are set to become operational within the next four years.
The site announcements came amid the Commerce Department’s push to allocate all the semiconductor manufacturing and research funds appropriated by the CHIPS and Science Act before President Joe Biden leaves office on Jan. 20. Since the November election, the department has awarded billions of dollars to Micron Technology, Intel, Taiwan Semiconductor Manufacturing Company, and other firms to spur the construction and modernization of chip fabrication facilities.
On Monday, the Commerce Department announced that the Advanced Packaging Piloting Facility (PPF) will be sited at the Arizona State University Research Park in Tempe, Arizona. The PPF aims to ease the scaling of new chips to full production by uniting activities “across the full technology stack for semiconductors,” from prototyping to packaging, in a single facility, according to the department’s facilities plan.
“This groundbreaking effort will mean that researchers and startups won’t need to go to China or Europe to test out their cutting-edge prototype microchips—they’ll be able to do that right here in America,” Sen. Mark Kelly (D-AZ) said in a press release. “The United States must lead the way in semiconductor research and development, and there’s nowhere more appropriate for it than Arizona.”
The prototyping capability will initially focus on advanced computing, including training and inferencing of AI models, according to the facilities plan. The PPF’s prototyping capabilities will also support research towards future materials and device innovations in interconnect and embedded memory, the plan adds.
The other two flagship facilities, whose expected sites were announced in the fall, are the Design and Collaboration Facility in California and the Extreme Ultraviolet Accelerator in New York.
The Design and Collaboration Facility will be based in Sunnyvale in Silicon Valley and will host programmatic activities such as the Workforce Center of Excellence, as well as research capabilities in chip design, electronic design automation, chip and system architecture, and hardware security.
The Extreme Ultraviolet Accelerator will provide access to EUV technology with standard numerical aperture capabilities by 2025 and higher ones by 2026. Higher NA allows for more intricate printing on a transistor so that more transistors can fit on one chip wafer, giving each chip greater processing power. The Commerce Department and Natcast said they will initially spend up to $825 million on equipment, EUV R&D, and the NSTC offices and support services in Albany.
The California administrative and design facility is planned to become operational in 2025, the New York EUV facility in 2026, and the Arizona PPF in 2028. The Commerce Department and Natcast also plan to announce information about the selection process for NSTC-affiliated technical centers in the coming months, according to the press release. These centers will aim to fill in gaps from the flagship facilities, potentially by providing access to specialized technologies like compound semiconductors, micro-electromechanical systems, and advanced lithography.
“By the decade’s end, the NSTC should be viewed throughout the world as a vital membership community with stakeholders and resources across the semiconductor ecosystem, including state-of-the-art facilities, effective programs, a network of respected scientists and engineers, and demonstrated technical achievements,” the NSTC strategic plan reads.
Some of President-elect Donald Trump’s advisors have floated the idea of clawing back CHIPS funds in the upcoming administration. Vivek Ramaswamy, who Trump tapped to lead the planned “Department of Government Efficiency,” described the recently announced rounds of CHIPS funding as “wasteful subsidies” and pledged to “review every one of these 11th-hour gambits.”
