A quantum information processor combination method to reduce latency with qubit readout and control
A quantum information processor combination method to reduce latency with qubit readout and control lead image
Physicists at Raytheon BBN Technologies in Massachusetts have tackled the challenge of building a large-scale quantum information processor with control hardware capable of executing quantum circuits with feedback by constructing two key components for qubit readout and control, the Quantum Digital Signal Processing (QDSP) framework and Arbitrary Pulse Sequencer 2 (APS2), respectively. They validated them with several quantum programs requiring feedback and/or feedforward within the qubit coherence times. They report their findings in Review of Scientific Instruments.
The authors described how QDSP converts qubit readout pulses into 0 and 1 state assignments with custom Field Programmable Gate Array (FPGA) gateware. Their design balances several considerations for channel filter design, including latency, crosstalk, and numerical stability. The researchers achieved significant latency reduction by combining several signal processing steps into one module.
The APS2 is an arbitrary waveform generator that achieves arbitrary control flow by incorporating aspects of CPU design. In place of a sequence table, the researchers realized an op-code architecture with an instruction set containing commands for waveform output, looping, and branching based upon real-time information. They executed these instructions with a superscalar architecture that maintains deterministic timing of several components.
To validate their system, the authors demonstrated active qubit initialization, measurement-based S and T gates, and entanglement generation through measurement, each of which require feedback/forward of qubit measurements. For example, the researchers implemented S and T gates by conditioning Z(π) rotations on a target qubit with measurement of an ancilla.
According to the paper, the authors’ next steps for their system include integration control and readout into a unified hardware system, improvements to the APS2 analog output chain, and generalized system synchronization.
Source: “Hardware for dynamic quantum computing,” by Colm A. Ryan, Blake R. Johnson, Diego Ristè, Brian Donovan, and Thomas A. Ohki, Review of Scientific Instruments (2017). The article can be accessed at https://doi.org/10.1063/1.5006525 .
